`timescale 1ns/1ps
module fir_top_tb();


    parameter DATAIN_WIDTH = 16;
    parameter DATAOUT_WIDTH = 32;
    parameter CLOCK_SAMPLE   = 100;  //10M
    parameter ClOCK_WORK     = 50 ;  //20M
    parameter LEN = 10;

    reg rst_n,sys_clk,sample_clk;
    reg wr_en,rd_en;
    reg [DATAIN_WIDTH-1:0] data_i;

    wire [DATAOUT_WIDTH-1:0] data_o;

    integer i,k;
    reg signed [11:0]stimulus[1023:0];

    initial begin
        // $readmemh("../matlab_sim/memh.txt",stimulus);
        $readmemh("D://Project//test//fir_test//matlab_sim//memh_1m_3m.txt",stimulus);
        i=0;
        k=0;
        for(k = 0;k < LEN;k = k+1) begin
            repeat(1024) begin
                // i=i+1;
                data_i = {{4{stimulus[i][11]}},stimulus[i]};
                i=i+1;
                #(ClOCK_WORK) ;
            // #32            //32M
                            
            end
            i=0;
        end
        
    
    end

    initial begin
        rd_en   = 1'b0;
        wr_en   = 1'b0;
        sys_clk = 1'b1;
        sample_clk = 1'b1;
        rst_n   = 1'b1;
        #(CLOCK_SAMPLE*10) 
        // #(32*6)
        rst_n   = 1'b0;
        #(CLOCK_SAMPLE*12)
        // #(32*10)
        rst_n   = 1'b1;
        #(CLOCK_SAMPLE*60) wr_en = 1'b1;
        #(CLOCK_SAMPLE*20) rd_en = 1'b1;

    end

    always #(ClOCK_WORK/2) sys_clk = ~sys_clk;
    always #(CLOCK_SAMPLE/2) sample_clk = ~sample_clk;
    // always #16 sys_clk = ~sys_clk;


    fir_top 
#(
    .DATAIN_WIDTH  (16),
    .DATAOUT_WIDTH (32)
)
u_fir_top(
    .rst_n      (rst_n),            //reset signal
    .fir_clk    (sys_clk),          //fir working clock
    
    .wr_clk     (sys_clk),
    .data_in    (data_i ),
    .wr_en      (wr_en  ),

    .rd_clk     (sys_clk),
    .data_out   (data_o ),
    .rd_en      (rd_en)
);

endmodule